This unit aims to develop the required engineering skills to design and implement an integrated circuit design with emphasis on the front-end design skills.

The objectives of this unit are to expose students to techniques and design methodology in Integrated Circuit. Students will develop skills in Modeling, simulation, verification, testing and implementation using industry standard EDA tools. Upon satisfactory completion of this subject, students should be able to carry out the design of an integrated circuit from requirement analysis through to implementation.

To achieve this, the student will:

Understand the design flow of an integrated circuit and its constraints.
Understand Hardware Description Modeling, synthesis algorithms and tradeoff between area, power and speed constrains.
Become familiar with the implementation strategies, Static and dynamic testing of IC circuit
Understand the constraints and Implementation of Built In Self Test
Become familiar with a range of design methodologies through their application

Teaching Methods:

Lectures (48 lectures) and Practical Work (18 hours)

Assessment:

Examination (60-70%), tests (0-10%), Practical work (20-30%)

Generic Skills Outcomes:

In this unit, students are expected to enhance the Key Generic Skills below as recognised by Engineers Australia. The Unit Outline explains how these outcomes will be achieved.

Ability to apply knowledge of basic science and engineering fundamentals
Ability to communicate effectively, not only with engineers but also with the community at large
Ability to undertake problem identification, formulation and solution
Ability to utilize a systems approach to design and operational performance
Ability to function effectively as an individual and in a multi-disciplinary and multi-cultural teams, with the capacity to be a leader or manager as well as an effective team member
Expectation of the need to undertake lifelong learning, and capacity to do so

Content:

Microelectronics design methodologies (ASIC and FPGA).
Issues involved in high level synthesis.
Hardware description language (VHDL) features.
VHDL modelling techniques: structural and behavioural models.
System implementation strategies.
Technology-independent design.
State machine VHDL description and synthesis.
Hardware testing and design for testability.
Design examples.
Design methodology for high level synthesis.
Partitioning in high-level synthesis.
Algorithmic synthesis.
Scheduling formulation and allocation.

References:

Perry, D, VHDL, McGraw Hill.
Armstrong, J & Gary, F, Structured Logic Design with VHDL, Prentice Hall.
Bhasker, J, A VHDL Primer, Prentice Hall.
Sjoholm, S & Lindh, L, VHDL for Designers, Prentice Hall, 1997.
Pellerin, D & Taylor, D, VHDL Made Easy, Prentice Hall, 1997.
IEEE Design & Test of Computer Magazine.
IEEE Transaction on Computer-Aided Design.

Integrated Circuit Design

Unit Code: HET378

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